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Li, H.; Wang, Z. A 13-bit 160MS/s pipelined subranging-SAR ADC with low-offset dynamic comparator. In Proceedings of the 2017 IEEE Asian Solid-State Circuits Conference (A-SSCC), Seoul, Republic of Korea, 6–8 November 2017. [Google Scholar]Chen, Y.; Wang, Z.; Zhuang, Y.; Tang, H. Analysis and Design of Sigma-Delta ADCs for Automotive Control Systems. In Proceedings of the 2021 IEEE 3rd International Conference on Circuits and Systems (ICCS), Chengdu, China, 29–31 October 2021. [Google Scholar]Pei, R.; Liu, J.; Tang, X.; Li, F.; Wang, Z. A low-offset dynamic comparator with input offset-cancellation. In Proceedings of the 2017 IEEE 12th International Conference on ASIC (ASICON), Guiyang, China, 25–28 October 2017. [Google Scholar]Fan, X.P.; Chan, P.K. A CMOS high-speed multistage preamplifier for comparator design. In Proceedings of the 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No. 04CH37512), Vancouver, BC, Canada, 23–26 May 2004. [Google Scholar]Lee, M.J.; Dally, W.J.; Chiang, P. Low-power area-efficient high-speed I/O circuit techniques. IEEE J. Solid-State Circuits 2000, 35, 1591–1599. [Google Scholar] [CrossRef]Jung, H.; Youn, E.; Jang, Y.C. An 11-Bit 10 MS/s SAR ADC with C–R DAC Calibration and Comparator Offset Calibration. Electronics 2022, 11, 3654. [Google Scholar] [CrossRef]Xu, Y.; Belostotski, L.; Haslett, J.W. Offset-corrected 5GHz CMOS dynamic comparator using bulk voltage trimming: Design and analysis. In Proceedings of the 2011 IEEE 9th International New Circuits and Systems Conference, Bordeaux, France, 26–29 June 2011. [Google Scholar]Wang, S.-H.; Hung, C.-C. A 0.3V 10b 3MS/s SAR ADC with Comparator Calibration and Kickback Noise Reduction for Biomedical Applications. IEEE Trans. Biomed. Circuits Syst. 2020, 14, 558–569. [Google Scholar] [PubMed]Lee, J.; Lim, Y.; Sung, B.; Oh, S.; Chun, J.H.; Lee, J. An Effective Transconductance Controlled Offset Calibration for Dynamic Comparators. In Proceedings of the 2020 IEEE International Symposium on Circuits and Systems (ISCAS), Seville, Spain, 10–21 October 2020. [Google Scholar]Mohammadi, M.; Sadeghipour, K.D. A 0.5V 200 MHz offset trimmable latch comparator in standard 0.18 um CMOS process. In Proceedings of the 2013 21st Iranian Conference on Electrical Engineering (ICEE), Mashhad, Iran, 14–16 May 2013. [Google Scholar]Verma, D.; Shehzad, K.; Khan, D.; Kim, S.J.; Pu, Y.G.; Yoo, S.-S.; Hwang, K.C.; Yang, Y.; Lee, K.-Y. A Design of Low-Power 10-bit 1-MS/s Asynchronous SAR ADC for DSRC Application. Electronics 2020, 9, 1100. [Google Scholar] [CrossRef]Baek, S.-Y.; Lee, J.-K.; Ryu, S.-T. An 88-dB max-SFDR 12-bit SAR ADC with speed enhanced ADEC and dual registers. IEEE Trans. Circuits Syst. II Exp. Briefs 2013, 60, 562–566. [Google Scholar] [CrossRef]Behzad, R. Download Amazon International Price Comparator latest version for Windows free. Amazon International Price Comparator latest update: Design of Analog CMOS Integrated Circuits; Mc-Graw Hill Inc.: New York, NY, USA, 2015. [Google Scholar]Hesham, O. Fast and accurate technique for comparator offset voltage simulation. Microelectron. J. 2019, 89, 91–97. [Google Scholar]Peng, X.; Gao, A.; Chen, Z.; Zhang, H.; Li, Y.; Cao, W.; Liu, X.; Tang, H. A Novel Comparator Offset Calibration Technique for SAR ADCs. In Proceedings of the 2018 IEEE International Conference on Electron Devices and Solid State Circuits (EDSSC), Shenzhen, China, 6–8 June 2018. [Google Scholar]Zhang, Y.; Cai, J.; Li, X.; Zhang, Y.; Su, B. A 3.66 μW 12-bit 1 MS/s SAR ADC with mismatch and offset foreground calibration. Microelectron. J. 2021, 116, 105–244. [Google Scholar] [CrossRef] Figure 1. The structure of the proposed self-calibration comparator applied in an SAR ADC system. Figure 1. The structure of the proposed self-calibration comparator applied in an SAR ADC system. Figure 2. The common-mode buffer. Figure 2. The common-mode buffer. Figure 3. The symmetrical OTA. Figure 3. The symmetrical OTA. Figure 4. Differential preamplifier Ai (i = 0, 2, …, 5, 6). Figure 4. Differential preamplifier Ai (i = 0, 2, …, 5, 6). Figure 5. Comparator offset cancellation techniques: (a) the output offset storage; (b) the input offset storage. Figure 5. Comparator offset cancellation techniques: (a) the output offset storage; (b) the input offset storage. Figure 6. Differential preamplifier with offset voltage. Figure 6. Differential preamplifier with offset voltage. Figure 7. The first-stage preamplifier A0 with offset trimming circuits. Figure 7. The first-stage preamplifier A0 with offset trimming circuits. Figure 8. Control logic circuit. Figure 8. Control logic circuit. Figure 9. Circuit implementation of the switches S0, S1, and S2. Figure 9. Circuit implementation of the switches S0, S1, and S2. Figure 10. The timing diagram of comparator offset trimming. Figure 10. The timing diagram of comparator offset trimming. Figure 11. The layout of the comparator. Figure 11. The layout of the comparator. Figure 12. Amplitude–frequency response curves of all amplifiers. (a) preamplifier A0; (b) preamplifier Ai (i = 1, 2, …, 5, 6); (c) OTA. Figure 12. Amplitude–frequency response curves of all amplifiers. (a) preamplifier A0; (b) preamplifier Ai (i = 1, 2, …, 5, 6); (c) OTA. Figure 13. Transient simulation test bench of the proposed comparator. Figure 13. Transient simulation test bench of the proposed comparator. Figure 14. Transient simulation curves of the proposed comparator (ripple = 30 μV). Figure 14. Transient simulation curves ofComments
Li, H.; Wang, Z. A 13-bit 160MS/s pipelined subranging-SAR ADC with low-offset dynamic comparator. In Proceedings of the 2017 IEEE Asian Solid-State Circuits Conference (A-SSCC), Seoul, Republic of Korea, 6–8 November 2017. [Google Scholar]Chen, Y.; Wang, Z.; Zhuang, Y.; Tang, H. Analysis and Design of Sigma-Delta ADCs for Automotive Control Systems. In Proceedings of the 2021 IEEE 3rd International Conference on Circuits and Systems (ICCS), Chengdu, China, 29–31 October 2021. [Google Scholar]Pei, R.; Liu, J.; Tang, X.; Li, F.; Wang, Z. A low-offset dynamic comparator with input offset-cancellation. In Proceedings of the 2017 IEEE 12th International Conference on ASIC (ASICON), Guiyang, China, 25–28 October 2017. [Google Scholar]Fan, X.P.; Chan, P.K. A CMOS high-speed multistage preamplifier for comparator design. In Proceedings of the 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No. 04CH37512), Vancouver, BC, Canada, 23–26 May 2004. [Google Scholar]Lee, M.J.; Dally, W.J.; Chiang, P. Low-power area-efficient high-speed I/O circuit techniques. IEEE J. Solid-State Circuits 2000, 35, 1591–1599. [Google Scholar] [CrossRef]Jung, H.; Youn, E.; Jang, Y.C. An 11-Bit 10 MS/s SAR ADC with C–R DAC Calibration and Comparator Offset Calibration. Electronics 2022, 11, 3654. [Google Scholar] [CrossRef]Xu, Y.; Belostotski, L.; Haslett, J.W. Offset-corrected 5GHz CMOS dynamic comparator using bulk voltage trimming: Design and analysis. In Proceedings of the 2011 IEEE 9th International New Circuits and Systems Conference, Bordeaux, France, 26–29 June 2011. [Google Scholar]Wang, S.-H.; Hung, C.-C. A 0.3V 10b 3MS/s SAR ADC with Comparator Calibration and Kickback Noise Reduction for Biomedical Applications. IEEE Trans. Biomed. Circuits Syst. 2020, 14, 558–569. [Google Scholar] [PubMed]Lee, J.; Lim, Y.; Sung, B.; Oh, S.; Chun, J.H.; Lee, J. An Effective Transconductance Controlled Offset Calibration for Dynamic Comparators. In Proceedings of the 2020 IEEE International Symposium on Circuits and Systems (ISCAS), Seville, Spain, 10–21 October 2020. [Google Scholar]Mohammadi, M.; Sadeghipour, K.D. A 0.5V 200 MHz offset trimmable latch comparator in standard 0.18 um CMOS process. In Proceedings of the 2013 21st Iranian Conference on Electrical Engineering (ICEE), Mashhad, Iran, 14–16 May 2013. [Google Scholar]Verma, D.; Shehzad, K.; Khan, D.; Kim, S.J.; Pu, Y.G.; Yoo, S.-S.; Hwang, K.C.; Yang, Y.; Lee, K.-Y. A Design of Low-Power 10-bit 1-MS/s Asynchronous SAR ADC for DSRC Application. Electronics 2020, 9, 1100. [Google Scholar] [CrossRef]Baek, S.-Y.; Lee, J.-K.; Ryu, S.-T. An 88-dB max-SFDR 12-bit SAR ADC with speed enhanced ADEC and dual registers. IEEE Trans. Circuits Syst. II Exp. Briefs 2013, 60, 562–566. [Google Scholar] [CrossRef]Behzad, R.
2025-03-27Design of Analog CMOS Integrated Circuits; Mc-Graw Hill Inc.: New York, NY, USA, 2015. [Google Scholar]Hesham, O. Fast and accurate technique for comparator offset voltage simulation. Microelectron. J. 2019, 89, 91–97. [Google Scholar]Peng, X.; Gao, A.; Chen, Z.; Zhang, H.; Li, Y.; Cao, W.; Liu, X.; Tang, H. A Novel Comparator Offset Calibration Technique for SAR ADCs. In Proceedings of the 2018 IEEE International Conference on Electron Devices and Solid State Circuits (EDSSC), Shenzhen, China, 6–8 June 2018. [Google Scholar]Zhang, Y.; Cai, J.; Li, X.; Zhang, Y.; Su, B. A 3.66 μW 12-bit 1 MS/s SAR ADC with mismatch and offset foreground calibration. Microelectron. J. 2021, 116, 105–244. [Google Scholar] [CrossRef] Figure 1. The structure of the proposed self-calibration comparator applied in an SAR ADC system. Figure 1. The structure of the proposed self-calibration comparator applied in an SAR ADC system. Figure 2. The common-mode buffer. Figure 2. The common-mode buffer. Figure 3. The symmetrical OTA. Figure 3. The symmetrical OTA. Figure 4. Differential preamplifier Ai (i = 0, 2, …, 5, 6). Figure 4. Differential preamplifier Ai (i = 0, 2, …, 5, 6). Figure 5. Comparator offset cancellation techniques: (a) the output offset storage; (b) the input offset storage. Figure 5. Comparator offset cancellation techniques: (a) the output offset storage; (b) the input offset storage. Figure 6. Differential preamplifier with offset voltage. Figure 6. Differential preamplifier with offset voltage. Figure 7. The first-stage preamplifier A0 with offset trimming circuits. Figure 7. The first-stage preamplifier A0 with offset trimming circuits. Figure 8. Control logic circuit. Figure 8. Control logic circuit. Figure 9. Circuit implementation of the switches S0, S1, and S2. Figure 9. Circuit implementation of the switches S0, S1, and S2. Figure 10. The timing diagram of comparator offset trimming. Figure 10. The timing diagram of comparator offset trimming. Figure 11. The layout of the comparator. Figure 11. The layout of the comparator. Figure 12. Amplitude–frequency response curves of all amplifiers. (a) preamplifier A0; (b) preamplifier Ai (i = 1, 2, …, 5, 6); (c) OTA. Figure 12. Amplitude–frequency response curves of all amplifiers. (a) preamplifier A0; (b) preamplifier Ai (i = 1, 2, …, 5, 6); (c) OTA. Figure 13. Transient simulation test bench of the proposed comparator. Figure 13. Transient simulation test bench of the proposed comparator. Figure 14. Transient simulation curves of the proposed comparator (ripple = 30 μV). Figure 14. Transient simulation curves of
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